1. Field of the Invention
The present invention relates to a method of forming a semiconductor layer and to a method of manufacturing a semiconductor device using the layer forming method. More particularly, the invention relates to a method for forming a boron doped amorphous or polysilicon layer or filler.
2. Description of the Related Art
Recent developments in high density integrated semiconductor devices such as DRAMs, for example, have required a corresponding increase in the density of electric circuit conductor elements and connectors used in the devices. For example, electrical conductor elements are formed in multiple layers, the conductor elements in one layer being insulated from those of an adjacent layer, for reduction in the area of DRAMS.
As a result of the multiple conductor element layers, many steps, projections or cavities are present on a substrate to be covered by material. Accordingly, materials used for the covering layers are required to provide good step coverage and be capable of application with uniform thickness. These characteristics are needed both for covering projections from the substrate and for materials used to fill a contact hole for electrical connection of overlying conductor wires or layers.
A boron doped polysilicon, formed by a thermal decomposition of silane (Si.sub.1 H.sub.4) and diborane (B.sub.2 H.sub.6), is conventionally used for such filling materials. The temperature during formation is usually kept to be about 500.degree.-600.degree. C., such that SiH.sub.4 can be decomposed. That is, SiH.sub.4 gas itself cannot be decomposed below that range of temperatures. The boron doped polysilicon is also used as electrodes of LSI, in addition to use as filling material, because the layer, formed by the thermal decomposition of these materials, has a good step coverage. For example, it is possible to fill the contact holes satisfactorily even if the contact hole has an aspect ratio (depth of groove/width of groove) more than 1. Also, the layer is free of voids after the formation. Further, the layer has a characteristic of low resistivity required by the devices.
The method of forming the boron doped layer as the filling material may be understood by reference to FIGS. 1(a)-1(d) of the accompanying drawings.
As shown in FIG. 1(a), a contact hole 100 is formed in a SiO.sub.2 layer 102 so as to expose a diffusion layer 104, formed on a silicon substrate 108. A gate electrode 106 is formed on the substrate 108 through a gate insulating layer 110. Moreover, a 50 nm thick titanium layer 112 and a 20 nm thick TiN layer 116 are formed on the SiO.sub.2 layer 102 and the diffusion layer 104. After formation, the layers 112 and 116 are annealed in a N.sub.2 atmosphere at 600.degree. C. for about 30 minutes, so as to form a 70 nm thick TiSi.sub.2 layer 114 at the interface of the diffusion layer 104 and the titanium layer 112.
As shown in FIG. 1(b), after formation of the layer 114, a boron doped polysilicon layer 118 is formed by the LPCVD method, so as to fill contact hole 100. The layer 118 is formed at a temperature of 500.degree.-600.degree. C. and at a pressure of 0.1 Torr, using SiH.sub.4 and B.sub.2 H.sub.6 as the source gas.
Thereafter, as shown in FIG. 1(c), a part of the boron doped polysilicon layer 118 formed on the SiO.sub.2 layer 102 is etched back by the RIE (Reactive Ion Etching) method. The titanium layer 112 and TiN layer 116 on the SiO.sub.2 layer 102 are removed at the same time.
After the etching, a 50 nm thick titanium layer 120 is formed on the whole surface of the substrate as a barrier layer against an aluminum layer to be formed. After formation, the layer 120 is annealed, at 600.degree. C. for 30 minutes, to form a 70 nm thick TiSi.sub.2 layer 122 at the interface with the polysilicon layer 118. A 20 nm thick TiN layer 124 is formed, followed by formation of the aluminum layer 126, using the sputter method, as shown FIG. 1(d).
According to this forming method, a resistivity of 3-5 m .OMEGA..cm can be obtained in the layer 118 of boron doped polysilicon without voids. However, the high temperature (500.degree.-600.degree. C.) required for processing the boron doped polysilicon layer 118 presents problems to the manufacturing process.
For example, an aluminum layer cannot be formed before the formation of the boron doped silicon layer 118, because it has a low melting point. A margin of the diffusion layer 104 for the expansion which is caused by the thermal process, is also needed.
Accordingly, a lower temperature for the CVD method being processed at lower temperature is required. The CVD method has disadvantages due to the manufacturing apparatus used for its practice. A vertical CVD apparatus as shown in FIG. 2 is used to make boron doped polysilicon layer, according to the CVD method.
As shown, the apparatus includes a cylindrical outer tube 11, a cylindrical inner tube 12 spaced from the outer tube, and a quartz port 14 placed in the center of the outer tube for holding a plurality of stacked substrates 18.
The temperature of the inner space of the apparatus is set to be 550.degree. C. by a pedestal block 13.
SiH.sub.4 gas and B.sub.2 H.sub.6 gas are introduced from gas introducing tubes 16a, 16b of a manifold 16. A cap 17 is provided at the bottom portion of the apparatus. In the operation of the apparatus, a boron doped polysilicon layer 118 is formed on each of the substrates.
The gases are caused to flow from the lower portion of the inner tube to the upper portion thereof, so as to be supplied to each substrate in the stack and the residual gases are exhausted from the upper portion of the inner tube 12 to the lower portion of the outer tube 11. The flow of the gases is generally perpendicular to the substrates. Although a plurality of substrates can be batch-processed with the CVD apparatus, it has serious disadvantages in that
(1) deviations in the resistivity of the deposited layer occur according to the positions at which the substrates are located because the concentration of boron is higher at the upper levels of gas flow than at lower levels; PA1 (2) the thickness of the boron doped polysilicon layer also varies, depending on the position of each substrate in that the layers deposited at the upper levels are thicker than the layers deposited at the lower levels of the stack; and PA1 (3) the uniformity of the layer on the surface of each substrate also deviates in thickness, that is, the thickness at the edge portion of the substrate is greater than that at the center portion.
These deviations lead to deteriorate the performance of the device. As a result, in order to form only high quality layers, the number of the substrates to be processed at once is limited to about 25-50 substrates. Actually, it is difficult, if not impossible, to process at once more than 100 substrates according to such the CVD apparatus to obtain even low quality layers.
Another use of boron doped polysilicon is as a layer formed on the sidewall of a metallic conductor to provide good contact with a contact hole connector to connect the metallic conductor electrically to an overlying conductor element. By forming the sidewall layer, even if a contact hole for the conductor element is misaligned, the connector can be formed to have good contact with both the upper and lower conductor elements.
The processes for forming such a connection is shown in FIG. 3(a)-3(e). As shown in FIG. 3(a), an amorphous silicon layer 300 is first formed on a lower aluminum conductor layer 302 previously formed on a substrate 304 covered by an SiO.sub.2 layer 306. The amorphous silicon layer 300 is etched back so as to remain on the side wall of the aluminum conductor 302 (FIG. 3(b)). After that, a SiO.sub.2 layer 308 is deposited by CVD as an interlayer insulator covering on the whole surface of the substrate and to have a substantially planar upper surface by using TEOS and O.sub.3 gases (FIG. 3(c)).
Then, as shown is FIG. 3(d), a contact hole 310 is formed by using a photo resist layer (not shown) as a mask, so as to expose the wire 302. Finally, and as shown in FIG. 3(e), a tungsten (W) filler is formed to provide a conductive connector 312 in the contact hole 310 by using WF.sub.6 and SiH.sub.4 as the source gases and an aluminum layer 314 is formed as a second conductor element on the tungsten filler 312.
In this method, the amorphous silicon layer 300 cannot be formed by using a silane (SiH.sub.4) or a disilane thermal decomposition method, because the first aluminum conductor layer 302 cannot withstand the temperature of the formation, such as more than 500.degree. C. So the amorphous silicon layer 300 is formed by the plasma CVD method, which can be carried out at temperatures below 300.degree. C. However, the layer formed by the plasma CVD does not have good step coverage and does not remain fully on the sidewall of the first conductor element 302, as shown in FIG. 3(e). As a result, when the contact hole 310 is formed, there is a likelihood that the SiO.sub.2 layer 306 becomes etched through and beyond the lower surface thereof as shown in FIG. 3(d). Therefore, good contact between the two conductors 302 and 314 is compromised and an electrical short is likely to be caused with an under conductive layer (not shown) on the substrate 304 because of the deep etch.